Cypress Semiconductor /psoc63 /PROT /SMPU /MS1_CTL

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Interpret as MS1_CTL

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (P)P0 (NS)NS 0PRIO 0 (PC_MASK_0)PC_MASK_0 0PC_MASK_15_TO_1

Description

Master 1 protection context control

Fields

P

See MS0_CTL.P.

NS

See MS0_CTL.NS.

PRIO

See MS0_CTL.PRIO

PC_MASK_0

See MS0_CTL.PC_MASK_0.

PC_MASK_15_TO_1

See MS0_CTL.PC_MASK_15_TO_1.

Links

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